SH7080_09 Datasheet, PDF (461/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
(3) On-Chip Peripheral Module Request Mode
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
The DMA receives ten transfer request signals in total: five compare match and input capture
interrupts from multi-function timer pulse unit 2 (MTU2), receive data full interrupts (RXI) and
transmit data empty interrupts (TXI) from two serial communication interface (SCI) channels, and
the A/D conversion end interrupt (ADI) from the A/D converter.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
The transfer request source does not need to be the data transfer source or destination. However,
when the transmit data empty transfer request (TXI) from the SCI is specified as the transfer
request source, the transfer destination must be the transmit data register (TDR) in the respective
SCI channel. Similarly, when the receive data full transfer request (RXI) in the SCI is specified as
the request source, the transfer source must be the receive data register (RDR) in the respective
SCI channel. When the A/D conversion end transfer request (ADI) is specified as the transfer
request source, the transfer source must be the respective register in the A/D converter.
Table 10.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
Transfer
Transfer
RS3 RS2 RS1 RS0 Request Source Request Signal Source
Destination Bus Mode
0 1 1 0 MTU2
TGIA_0
Any*
Any*
Burst or cycle steal
1 MTU2
TGIA_1
Any*
Any*
Burst or cycle steal
1 0 0 0 MTU2
TGIA_2
Any*
Any*
Burst or cycle steal
1 MTU2
TGIA_3
Any*
Any*
Burst or cycle steal
1 0 MTU2
TGIA_4
Any*
Any*
Burst or cycle steal
1 A/D_1
ADI1
ADDR4 to Any*
ADDR7
Cycle steal
1 0 0 SCI_0 transmitter TXI_0
Any*
SCTDR_0 Cycle steal
1 SCI_0 receiver RXI_0
SCRDR_0 Any*
Cycle steal
1 0 SCI_1 transmitter TXI_1
Any*
SCTDR_1 Cycle steal
1 SCI_1 receiver RXI_1
SCRDR_1 Any*
Cycle steal
Notes: MTU2: Multi-function timer pulse unit 2
SCI_0 and SCI_1: Serial communication interface channels 0 and 1
ADDR4 to ADDR7: A/D data register in A/D converter channel 1
SCTDR_0 and SCTDR_1: Transmit data registers in SCI_0 and SCI_1
SCRDR_0 and SCRDR_1: Receive data registers in SCI_0 and SCI_1
* An external memory, a memory-mapped external device, an on-chip memory, or an on-
chip peripheral module (except DMAC, DTC, BSC, and UBC)
Rev. 4.00 Dec. 15, 2009 Page 401 of 1558
REJ09B0181-0400