SH7080_09 Datasheet, PDF (792/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
Initial
Bit
Bit Name value R/W Description
5
TE
0
R/W Transmit Enable
Enables or disables the SCI serial transmitter.
0: Transmitter disabled*¹
1: Transmitter enabled*²
Notes: 1. The TDRE flag in SCSSR is fixed at 1.
2. Serial transmission starts after writing
transmit data into SCTDR and clearing the
TDRE flag in SCSSR to 0 while the
transmitter is enabled. Select the transmit
format in the serial mode register (SCSMR)
before setting TE to 1.
4
RE
0
R/W Receive Enable
Enables or disables the SCI serial receiver.
0: Receiver disabled*¹
1: Receiver enabled*²
Notes: 1. Clearing RE to 0 does not affect the receive
flags (RDRF, FER, PER, and ORER). These
flags retain their previous values.
2. Serial reception starts when a start bit is
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive
format in SCSMR before setting RE to 1.
3
MPIE
0
R/W Multiprocessor Interrupt Enable (only when MP = 1 in
SCSMR in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped and setting of the
RDRF, FER, and ORER status flags in SCSSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
to 0 and normal receiving operation is resumed. For
details, refer to section 15.4.4, Multiprocessor
Communication Function.
Rev. 4.00 Dec. 15, 2009 Page 732 of 1558
REJ09B0181-0400