SH7080_09 Datasheet, PDF (1287/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
Table 23.5 Register/Parameter and Target Mode
Initiali- Program-
RAM
Download zation ming
Erasure Read Emulation
Programming/ FCCS
√
erasing interface _FPCS
√
registers
PECS
√
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FKEY
√
FMATS —
—
√
—
√*¹
√
—
—
√*¹
√*²
—
FTDAR √
—
—
—
—
—
Programming/ DPFR
√
erasing interface _FPFR
—
parameters
FPEFEQ —
—
—
√
√
√
—
—
—
—
√
—
—
—
—
—
FUBRA —
√
—
—
—
—
FMPAR —
—
√
—
—
—
FMPDR —
—
√
—
—
—
FEBS
—
—
—
√
—
—
RAM emulation RAMER —
—
—
—
—
√
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
Rev. 4.00 Dec. 15, 2009 Page 1227 of 1558
REJ09B0181-0400