SH7080_09 Datasheet, PDF (211/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Bit
Bit Name
31 to 22 ⎯
Initial
Value R/W
All 0 R
21, 20 UTRGW[1:0] 00
R/W
19
UBIDB
0
R/W
18
⎯
0
R
17
UBIDA
0
R/W
16
⎯
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
UBCTRG Output Pulse Width Select
Select the UBCTRG output pulse width when the break
condition matches.
00: Setting prohibited.
01: UBCTRG output pulse width is 3 to 4 t
Bcyc
10: UBCTRG output pulse width is 7 to 8 t_Bcyc
11: UBCTRG output pulse width is 15 to 16 t_Bcyc
Note: t_Bcyc indicates the period of one cycle of the
external bus clock (Bφ = CK).
User Break Disable B
Enables or disables the user break interrupt request
when the channel B break conditions are satisfied.
0: User break interrupt request is enabled when break
conditions are satisfied
1: User break interrupt request is disabled when break
conditions are satisfied
Reserved
This bit is always read as 0. The write value should
always be 0.
User Break Disable A
Enables or disables the user break interrupt request
when the channel A break conditions are satisfied.
0: User break interrupt request is enabled when break
conditions are satisfied
1: User break interrupt request is disabled when break
conditions are satisfied
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 151 of 1558
REJ09B0181-0400