SH7080_09 Datasheet, PDF (565/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name value R/W Description
5
N
0
R/W Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
4
P
0
R/W Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
3
FB*
0
R/W External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out automatically
with the MTU2/channel 0 TGRA, TGRB, TGRC input
capture signals or by writing 0 or 1 to bits 2 to 0 in
TGCR.
0: Output switching is external input (Input sources are
channel 0 TGRA, TGRB, TGRC input capture signal)
1: Output switching is carried out by software (TGCR's
UF, VF, WF settings).
2
WF
1
VF
0
UF
0
R/W Output Phase Switch 2 to 0
0
R/W ^{These bits set the positive phase/negative phase output}
phase on or off state. The setting of these bits is valid
0
R/W _{only when the FB bit in this register is set to 1. In this}
case, the setting of bits 2 to 0 is a substitute for external
input. See table 11.39.
Note: * When the MTU2S is used to set the BDC bit to 1, do not set the FB bit to 0.
Rev. 4.00 Dec. 15, 2009 Page 505 of 1558
REJ09B0181-0400