SH7080_09 Datasheet, PDF (650/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Skipping counter 3ACNT 0
1
2
3
0
1
2
3
0
Skipping counter 4VCNT
0
1
2
3
0
1
2
3
Buffer transfer-enabled period
(T3AEN set to 1)
Buffer transfer-enabled period
(T4VEN set to 1)
Buffer transfer-enabled period
(T3AEN and T4VEN set to 1)
Note: Bits MD3 to MD0 in TMDR_3 are set to 1111, selecting buffer transfer at the crest and trough. The skipping count is set to three.
T3AEN and T4VEN are set to 1.
Figure 11.78 Relationship between Bits T3AEN and T4VEN in Timer Interrupt Skipping
Set Register (TITCR) and Buffer Transfer-Enabled Period
Rev. 4.00 Dec. 15, 2009 Page 590 of 1558
REJ09B0181-0400