SH7080_09 Datasheet, PDF (133/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Table 4.4 Frequency Division Ratios Specifiable with FRQCR
PLL
Multipli-
FRQCR Division Ratio
Setting
cation
Ratio Iφ Bφ Pφ MIφ MPφ Iφ
Clock Ratio
Clock Frequency (MHz)*
Input
Bφ Pφ MIφ MPφ Clock Iφ
Bφ Pφ MIφ MPφ
×8
1/8 1/8 1/8 1/8 1/8 1 1 1 1 1 10
10 10 10 10 10
1/4 1/8 1/8 1/8 1/8 2 1 1 1 1
20 10 10 10 10
1/4 1/8 1/8 1/4 1/8 2 1 1 2 1
20 10 10 20 10
1/4 1/4 1/8 1/8 1/8 2 2 1 1 1
20 20 10 10 10
1/4 1/4 1/8 1/4 1/8 2 2 1 2 1
20 20 10 20 10
1/4 1/4 1/8 1/4 1/4 2 2 1 2 2
20 20 10 20 20
1/4 1/4 1/4 1/4 1/4 2 2 2 2 2
20 20 20 20 20
1/3 1/3 1/3 1/3 1/3 8/3 8/3 8/3 8/3 8/3
26 26 26 26 26
1/2 1/8 1/8 1/8 1/8 4 1 1 1 1
40 10 10 10 10
1/2 1/8 1/8 1/4 1/8 4 1 1 2 1
40 10 10 20 10
1/2 1/8 1/8 1/2 1/8 4 1 1 4 1
40 10 10 40 10
1/2 1/4 1/8 1/8 1/8 4 2 1 1 1
40 20 10 10 10
1/2 1/4 1/8 1/4 1/8 4 2 1 2 1
40 20 10 20 10
1/2 1/4 1/8 1/4 1/4 4 2 1 2 2
40 20 10 20 20
1/2 1/4 1/8 1/2 1/8 4 2 1 4 1
40 20 10 40 10
1/2 1/4 1/8 1/2 1/4 4 2 1 4 2
40 20 10 40 20
1/2 1/4 1/4 1/4 1/4 4 2 2 2 2
40 20 20 20 20
1/2 1/4 1/4 1/2 1/4 4 2 2 4 2
40 20 20 40 20
1/2 1/2 1/8 1/8 1/8 4 4 1 1 1
40 40 10 10 10
1/2 1/2 1/8 1/4 1/8 4 4 1 2 1
40 40 10 20 10
1/2 1/2 1/8 1/4 1/4 4 4 1 2 2
40 40 10 20 20
1/2 1/2 1/8 1/2 1/8 4 4 1 4 1
40 40 10 40 10
1/2 1/2 1/8 1/2 1/4 4 4 1 4 2
40 40 10 40 20
1/2 1/2 1/8 1/2 1/2 4 4 1 4 4
40 40 10 40 40
1/2 1/2 1/4 1/4 1/4 4 4 2 2 2
40 40 20 20 20
1/2 1/2 1/4 1/2 1/4 4 4 2 4 2
40 40 20 40 20
1/2 1/2 1/4 1/2 1/2 4 4 2 4 4
40 40 20 40 40
Rev. 4.00 Dec. 15, 2009 Page 73 of 1558
REJ09B0181-0400