SH7080_09 Datasheet, PDF (282/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.3 Area Overview
9.3.1 Area Division
In the architecture, this LSI has 32-bit address spaces.
As listed in tables 9.2 to 9.15, this LSI can connect nine areas to each type of memory, and it
outputs chip select signals (CS0 to CS8) for each of them. CS0 is asserted during area 0 access. In
access to SDRAM connected to areas 2 and 3, signals such as RASx, CASx, RD/WR, and
DQMxx will be asserted. Furthermore, when the PCMCIA interface is selected in areas 5 and 6,
CE1A, CE1B, CE2A, and CE2B as well as CS5 and CS6 are asserted, according to the bytes to be
accessed.
9.3.2 Address Map
The external address space has a capacity of 1.5 Gbytes and is used by dividing into 9 spaces. The
memory to be connected and the data bus width are specified in each space. The address map for
the entire address space is listed in tables 9.2 to 9.15.
Table 9.2 Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode
Address
H'00000000 to
H'0003FFFF
H'00040000 to
H'01FFFFFF
H'02000000 to
H'03FFFFFF
Area
On-chip ROM
Reserved
CS0 space
H'04000000 to
H'0BFFFFFF
H'0C000000 to
H'0DFFFFFF
Reserved
CS3 space
Memory Type
Capacity
256 Kbytes
Bus
Width
32 bits
Normal space
SRAM with byte selection
Burst ROM (asynchronous)
Burst ROM (synchronous)
32 Mbytes
8 or 16
bits*
Normal space
SRAM with byte selection
SDRAM
32 Mbytes 8 or 16
bits*
Rev. 4.00 Dec. 15, 2009 Page 222 of 1558
REJ09B0181-0400