SH7080_09 Datasheet, PDF (855/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
7
C/A
0
R/W Communication Mode
Selects whether the SCIF operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W Character Length
Selects 7-bit or 8-bit data in asynchronous mode. In the
clock synchronous mode, the data length is always
eight bits, regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of
the transmit FIFO data register is not
transmitted.
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clock synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit
is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity
is checked according to the even/odd (O/E)
mode setting.
Rev. 4.00 Dec. 15, 2009 Page 795 of 1558
REJ09B0181-0400