SH7080_09 Datasheet, PDF (343/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
4
DMMTU4 0
R/W Enable Burst-Mode DMAC Transfer with TGIA_4
Activation Source
Setting this bit to 1 enables burst-mode DMA transfer
triggered by the TGIA_4 interrupt from MTU2.
0: DMA transfer in burst mode is disabled when TGIA_4
is the activation source.
1: DMA transfer in burst mode is enabled when TGIA_4
is the activation source.
Note: Clear this bit during DMA transfer in cycle-steal
mode.
3
DMMTU3 0
R/W Enable Burst-Mode DMAC Transfer with TGIA_3
Activation Source
Setting this bit to 1 enables burst-mode DMA transfer
triggered by the TGIA_3 interrupt from MTU2.
0: DMA transfer in burst mode is disabled when TGIA_3
is the activation source.
1: DMA transfer in burst mode is enabled when TGIA_3
is the activation source.
Note: Clear this bit during DMA transfer in cycle-steal
mode.
2
DMMTU2 0
R/W Enable Burst-Mode DMAC Transfer with TGIA_2
Activation Source
Setting this bit to 1 enables burst-mode DMA transfer
triggered by the TGIA_2 interrupt from MTU2.
0: DMA transfer in burst mode is disabled when TGIA_2
is the activation source.
1: DMA transfer in burst mode is enabled when TGIA_2
is the activation source.
Note: Clear this bit during DMA transfer in cycle-steal
mode.
Rev. 4.00 Dec. 15, 2009 Page 283 of 1558
REJ09B0181-0400