SH7080_09 Datasheet, PDF (329/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
17, 16
Bit Name
BW[1:0]
15 to 11 ⎯
10 to 7 W[3:0]
Initial
Value R/W
00
R/W
All 0 R
1010 R/W
Description
Number of Burst Wait Cycles
Specifies the number of wait cycles to be inserted into
the second or subsequent access cycles in burst
access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted into the
first burst access cycle or single access cycle.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 4.00 Dec. 15, 2009 Page 269 of 1558
REJ09B0181-0400