SH7080_09 Datasheet, PDF (374/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-2
Setting
BSZ[1:0]
A2ROW[1:0]/
A3ROW[1:0]
A2COL[1:0]/
A3COL[1:0]
10 (16 bits) 01 (12 bits)
10 (10 bits)
Output Pin of Row Address Column Address
This LSI
Output Cycle Output Cycle
SDRAM Pin
Function
A17
A27
A17
Unused
A16
A26
A16
A15
A25
A15
A14
A24*²
A24*²
A13
A23*²
A23*²
A13 (BA1)
A12 (BA0)
Specifies bank
A12
A22
A11
A21
A12
L/H*¹
A11
A10/AP
Address
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
Unused
Example of connected memory
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 4.00 Dec. 15, 2009 Page 314 of 1558
REJ09B0181-0400