SH7080_09 Datasheet, PDF (1606/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
17.4.7 Clock
Synchronous
Communication Mode
(4) Data
Transmission/Reception
Page
897
17.6.4 Note for
899
Reception Operations in
SSU Slave Mode
17.6.5 Note on Master 900
Transmission and Master
Reception Operations in
SSU Mode
17.6.6 Note on DTC
Transfers
18.3.2 I²C Bus Control 908
Register 2 (ICCR2)
Revision (See Manual for Details)
Description amended
When starting the transfer, confirm that the TEND, RDRF,
and ORER bits are cleared to 0 before setting the TE or RE
bits to 1.
If the value of RDRF is 1 when the 8th clock rises, ORER in
SSSR is set to 1, an overrun error occurs, and reception
halts. Receive operation is not possible while ORER is set to
1. To restart reception, first clear ORER to 0.
Newly added
Newly added
Newly added
Table amended
Bit Bit Name
7
BBSY
6
SCP
Initial
Value
0
1
R/W Description
R/W Bus Busy
This bit enables to confirm whether the I²C bus is
occupied or released and to issue start/stop conditions
in master mode. With the clock synchronous serial
format, this bit is always read as 0. With the I²C bus
format, this bit is set to 1 when the SDA level changes
from high to low under the condition of SCL = high,
assuming that the start condition has been issued. This
bit is cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high, assuming
that the stop condition has been issued. To issue a start
condition, simultaneously write 1 to BBSY and 0 to
SCP. Follow this procedure also when transmitting a
repeated start condition. To issue a stop condition,
simultaneously write 0 to BBSY and 0 to SCP.
R/W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, simultaneously write 1 to
BBSY and 0 to SCP. A repeated start condition is
issued in the same way. To issue a stop condition,
simultaneously write 0 to BBSY and 0 to SCP. This bit
is always read as 1. Even if 1 is written to this bit, the
data will not be stored.
Rev. 4.00 Dec. 15, 2009 Page 1546 of 1558
REJ09B0181-0400