SH7080_09 Datasheet, PDF (107/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
2.5.4 Logic Operation Instructions
Table 2.13 Logic Operation Instructions
Instruction
Operation
AND Rm,Rn
Rn & Rm → Rn
AND #imm,R0
R0 & imm → R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →
(R0 + GBR)
NOT Rm,Rn
~Rm → Rn
OR Rm,Rn
Rn | Rm → Rn
OR #imm,R0
R0 | imm → R0
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm →
(R0 + GBR)
TAS.B @Rn
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
TST Rm,Rn
Rn & Rm; if the result
is 0, 1 → T
TST #imm,R0
R0 & imm; if the result
is 0, 1 → T
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
if the result is 0, 1 → T
XOR Rm,Rn
Rn ^ Rm → Rn
XOR #imm,R0
R0 ^ imm → R0
XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm →
(R0 + GBR)
Code
Execution
Cycles T Bit
0010nnnnmmmm1001 1
⎯
11001001iiiiiiii 1
⎯
11001101iiiiiiii 3
⎯
0110nnnnmmmm0111 1
⎯
0010nnnnmmmm1011 1
⎯
11001011iiiiiiii 1
⎯
11001111iiiiiiii 3
⎯
0100nnnn00011011 4
Test result
0010nnnnmmmm1000 1
Test result
11001000iiiiiiii 1
Test result
11001100iiiiiiii 3
Test result
0010nnnnmmmm1010 1
⎯
11001010iiiiiiii 1
⎯
11001110iiiiiiii 3
⎯
Rev. 4.00 Dec. 15, 2009 Page 47 of 1558
REJ09B0181-0400