SH7080_09 Datasheet, PDF (830/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register
(SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is
0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is
started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and
then the TXD pin holds the states.
If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 15.11 shows an example of SCI transmit operation.
Transfer direction
Synchronization
clock
Serial data
LSB
Bit 0
Bit 1
MSB
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt Data written to SCTDR
TXI interrupt
request
and TDRE flag cleared
request
to 0 by TXI interrupt handler
One frame
Figure 15.11 Example of SCI Transmit Operation
TEI interrupt
request
Rev. 4.00 Dec. 15, 2009 Page 770 of 1558
REJ09B0181-0400