SH7080_09 Datasheet, PDF (1323/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
(3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 23.12.
Start erasing procedure
program
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(3.1)
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
Clear FKEY to 0
DPFR = 0?
Yes
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR setting+32
FPFR=0 ?
No
Yes _{Initialization error processing}
1
1
Set FKEY to H'5A
Set FEBS parameter
(3.2)
Erasing
JSR FTDAR setting+16 (3.3)
FPFR=0 ?
(3.4)
No
Yes _{Clear FKEY and erasing}
error processing
No
Required block
erasing is
completed?
(3.5)
Yes
Clear FKEY to 0
(3.6)
End erasing
procedure program
Figure 23.12 Erasing Procedure
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 23.9.2, Areas for Storage of the Procedural
Program and Data for Programming.
The frequency division ratio of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock
(Pφ) is specified as ×1/4 (initial value) by the frequency control register (FRQCR).
Rev. 4.00 Dec. 15, 2009 Page 1263 of 1558
REJ09B0181-0400