SH7080_09 Datasheet, PDF (1602/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
15.3.8 Serial Port
Register (SCSPTR)
Page
741
15.4.3 Clock
774
Synchronous Mode
Figure 15.14 Sample
Flowchart for
Transmitting/Receiving
Serial Data
Revision (See Manual for Details)
Table description amended
Initial
Bit
Bit Name value
R/W Description
0
SPB0DT 1
R/W Serial Port Break Data
Together with the SPB0IO bit and TE bit in SCSCR,
controls the TXD pin. Note that the TXD pin function
needs to have been selected with the pin function
controller (PFC).
Figure amended
No
RDRF = 1?
Yes
Read receive data in SCRDR, and
clear RDRF flag in SCSSR to 0
No
All data received?
Yes
Clear TE and RE bits in SCSCR to 0
15.5 SCI Interrupt
781
Sources and DMAC/DTC
End of transmission and reception
Description amended
When the ORER, FER, or PER flag in SCSSR is set to 1, an
ERI interrupt request is generated. This request cannot be
used to activate the DMAC or DTC.
It is possible to disable generation of RXI interrupt requests
and allow only ERI interrupt requests to be generated during
data reception processing. To accomplish this, set the RIE bit
to 1 and the EIO bit in SCSPTR to 1. Note that setting the
EIO bit to 1 will prevent the DMAC or DTC from transferring
received data because no ERI interrupt requests are
generated.
Rev. 4.00 Dec. 15, 2009 Page 1542 of 1558
REJ09B0181-0400