SH7080_09 Datasheet, PDF (447/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Channel Register Name
Abbrevia-
tion
R/W
3
DMA source
SAR_3
R/W
address register_3
DMA destination DAR_3
R/W
address register_3
DMA transfer count DMATCR_3 R/W
register_3
DMA channel
CHCR_3 R/W
control register_3
Common DMA operation
register
DMAOR R/W
Bus function
BSCEHR R/W
extending register
Initial value
H'00000000
H'00000000
H'00000000
H'00000000
H'0000
H'0000
Address
H'FFFFEB50
H'FFFFEB54
H'FFFFEB58
H'FFFFEB5C
H'FFFFEB60
H'FFFFE89A
Access Size
16, 32
16, 32
16, 32
8, 16, 32
8, 16
8, 16
10.3.1 DMA Source Address Registers_0 to _3 (SAR_0 to SAR_3)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address. When the data is
transferred from an external device with the DACK in single address mode, the SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined.
Bit: 31
-
Initial value: 0
R/W: R/W
30
-
0
R/W
29
-
0
R/W
28
-
0
R/W
27
-
0
R/W
26
-
0
R/W
25
-
0
R/W
24
-
0
R/W
23
-
0
R/W
22
-
0
R/W
21
-
0
R/W
20
-
0
R/W
19
-
0
R/W
18
-
0
R/W
17
-
0
R/W
16
-
0
R/W
Bit: 15
-
Initial value: 0
R/W: R/W
14
-
0
R/W
13
-
0
R/W
12
-
0
R/W
11
-
0
R/W
10
-
0
R/W
9
-
0
R/W
8
-
0
R/W
7
-
0
R/W
6
-
0
R/W
5
-
0
R/W
4
-
0
R/W
3
-
0
R/W
2
-
0
R/W
1
-
0
R/W
0
-
0
R/W
Rev. 4.00 Dec. 15, 2009 Page 387 of 1558
REJ09B0181-0400