SH7080_09 Datasheet, PDF (974/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.3.5 I²C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
Bit: 7
6
5
4
3
2
1
TDRE TEND RDRF NACKF STOP AL/OVE AAS
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
0
ADZ
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
TDRE
0
R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When the start condition (including retransmission)
is issued
• When slave mode is changed from receive mode to
transmit mode
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to ICDRT
• DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
6
TEND
0
R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I²C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clock synchronous serial format
[Clearing conditions]
• When 0 is written to TEND after reading TEND = 1
• When data is written to ICDRT
• DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
Rev. 4.00 Dec. 15, 2009 Page 914 of 1558
REJ09B0181-0400