SH7080_09 Datasheet, PDF (162/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 5 Exception Handling
5.8 Usage Notes
5.8.1 Value of Stack Pointer (SP)
The SP value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.2 Value of Vector Base Register (VBR)
The VBR value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling
When the SP value is not a multiple of 4, an address error will occur when stacking for exception
handling (interrupts, etc.) and address error exception handling will start after the first exception
handling is ended. Address errors will also occur in the stacking for this address error exception
handling. To ensure that address error exception handling does not go into an endless loop, no
address errors are accepted at that point. This allows program control to be passed to the handling
routine for address error exception and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. When stacking the SR and PC values, the SP values for both are subtracted by 4,
therefore, the SP value is still not a multiple of 4 after the stacking. The address value output
during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is
undefined.
Rev. 4.00 Dec. 15, 2009 Page 102 of 1558
REJ09B0181-0400