SH7080_09 Datasheet, PDF (687/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data before write.
Figure 11.124 shows the timing in this case.
TGR write cycle
T1
T2
MPφ
Address
Buffer register
address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
Buffer register write data
N
M
TGR
N
Figure 11.124 Contention between Buffer Register Write and Compare Match
Rev. 4.00 Dec. 15, 2009 Page 627 of 1558
REJ09B0181-0400