SH7080_09 Datasheet, PDF (917/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.7.6 Module Standby Mode Setting
The SCIF operation can be disabled or enabled using the standby control register. The initial
setting is for SCIF operation to be halted. Access to registers is enabled by clearing module
standby mode. For details, refer to section 26, Power-Down Modes.
16.7.7 Note on Using DTC
When data is written to SCFTDR by activating the DTC through a TXIF interrupt, the TEND flag
value is undefined. In this case, do not use the TEND flag as a transmit end flag.
16.7.8 FER Flag and PER Flag of Serial Status Register (SCFSR)
The FER flag and PER flag in the serial status register (SCFSR) are status flags that apply to next
entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DTC reads the
receive FIFO data register, the flags of framing errors and parity errors will disappear.
To check the received data for the states of framing errors and parity errors, only read the receive
FIFO register after reading the serial status register.
Rev. 4.00 Dec. 15, 2009 Page 857 of 1558
REJ09B0181-0400