SH7080_09 Datasheet, PDF (314/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
18 to 16 WW[2:0] 000
R/W Number of Wait Cycles in Write Access
Specify the number of cycles required for write access.
000: The same cycles as WR3 to WR0 settings (read
access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12, 11 SW[1:0] 00
R/W Number of Delay Cycles from Address and CSn
Assertion to RD and WRxx Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WRxx assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Dec. 15, 2009 Page 254 of 1558
REJ09B0181-0400