SH7080_09 Datasheet, PDF (351/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
T1
T2
T1
T2
CK
A29 to A0
CSn
RDWR
Read
RD
D15 to D0
Write
WRxx
D15 to D0
BS
DACKn*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 1
(Access Wait = 0, Cycle Wait = 0)
Rev. 4.00 Dec. 15, 2009 Page 291 of 1558
REJ09B0181-0400