SH7080_09 Datasheet, PDF (1608/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
Page
19.4.7 2-Channel
967
Scanning
Figure 19.4 Example of
2-Channel Scanning
23.5.2 User Program
Mode
1266
(3) Erasing Procedure in
User Program Mode
23.9.1 Specifications of
the Standard Serial
Communications
Interface in Boot Mode
1289
(2) Device selection
26.3.7 RAM Control
Register (RAMCR)
1337
Revision (See Manual for Details)
Figure amended
A/D conversion end (ADF)
CONADF bit in ADCSR = 0
CONADF bit in ADCSR = 1
Description amended
• Be sure to initialize both the erasing program and
programming program.
Initialization by setting the FPEFEQ and FUBRA
parameters must be performed for both the erasing
program and the programming program. Initialization
must be executed for both entry addresses: (download
start address for erasing program) + 32 bytes
(H'FFFF9020 in this example) and (download start
address for programming program) + 32 bytes
(H'FFFFB020 in this example).
Description amended
⎯ Size (1 byte): Number of characters in the device code
(fixed at 4)
Table amended
Bit: 7
6
5
4
3
2
1
0
-
-
- RAME -
-
-
-
Initial value: 0
0
0
1
0
0
0
-
R/W: R
R
R R/W R
R
R
R
Bit
Bit Name
3 to 1 ⎯
0
⎯
Initial
Value
R/W Description
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
Undefi ned R
Reserved
The read value is undefined. The write value should
always be 0.
26.8.2 Deep Software 1343
Standby Mode
28.2 DC Characteristics 1404 to
28.3 AC Characteristics 1475
28.4 A/D Converter
Characteristics
28.5 Flash Memory
Characteristics
Description deleted
Table conditions amended
4.5 V → 4.0 V
Rev. 4.00 Dec. 15, 2009 Page 1548 of 1558
REJ09B0181-0400