SH7080_09 Datasheet, PDF (768/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 13 Port Output Enable (POE)
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
High-impedance
state*
When low level is
Flag set
sampled at all points ¹
2
3
16 _{(POE received)}
When high level is
sampled at least once
1
2
13 Flag not set
Note: * Other high-current pins also go to the high-impedance state at the same timing.
Figure 13.3 Low-Level Detection Operation
13.4.2 Output-Level Compare Operation
Figure 13.4 shows an example of the output-level compare operation for the combination of
TIOC3B and TIOC3D. The operation is the same for the other pin combinations.
Pφ
PE9/
TIOC3B
PE11/
TIOC3D
Low level overlapping detected
High impedance state
Figure 13.4 Output-Level Compare Operation
Rev. 4.00 Dec. 15, 2009 Page 708 of 1558
REJ09B0181-0400