SH7080_09 Datasheet, PDF (328/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
19
MPXMD
0
R/W Burst MPX-I/O Interface Mode Specification
This bit specifies the number of bursts per access. This
setting has effect only when the DMAC is set to the 16-
byte transfer unit size. When other transfer unit size is
selected, the setting of the MPXMD bit is ignored and
there is always one burst per access.
0: Four bursts per access
Four consecutive data cycles occur after the
address cycle.
1: Two bursts per access
Two consecutive data cycles occur after the
address cycle.
The correspondence between the data (D31 to D29)
output in the address cycle and the transfer size is
shown below.
D31 D30 D29 Transfer Size
0
0
0
Byte (one byte)
0
0
1
Word (two bytes)
0
1
0
Longword (four bytes)
0
1
1
Quadword (eight bytes)
(only when MPXMD = 1)
1
0
0
16 bytes (only when
MPXMD = 0)
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
18
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 268 of 1558
REJ09B0181-0400