SH7080_09 Datasheet, PDF (340/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
14
CSSTP1 0
R/W Select Bus Release on NOP Cycle Generation by DTC
Specifies whether or not the bus is released in response
to requests from the CPU for external space access on
generation of the NOP cycle that follows reading of the
vector address.
If, however, the CSSTP2 bit is 1, bus mastership is
retained until all transfer is complete, regardless of the
setting of this bit.
0: The bus is released on generation of the NOP cycle by
the DTC.
1: The bus is not released on generation of the NOP
cycle by the DTC.
13
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
12
CSSTP2 0
R/W Select Bus Release during Burst-Mode-DMAC/DTC
Transfer
This setting applies to DTC transfer when the DTLOCK
bit is 0 and burst-mode DMAC transfer when the DMAC
is in channel-fixed mode, and the activating request was
an external request or was from MTU2. The value
specifies whether the bus mastership is or is not to be
released after each round of transfer in response to a
request from the CPU for access to the external space.
• DMAC transfer
0: Release the bus after each round of data transfer.
1: Only release the bus after all data transfer is complete.
Note: In round-robin mode, the bus is only released after
all data transfer is complete, regardless of the
setting of this bit.
• DTC transfer
0: When the DTLOCK and CSSTP1 bits are 0, the bus is
released on generation of the NOP cycle after reading
of the vector address. When the DTLOCK bit is 0 and
the CSSTP1 bit is 1, the bus is released after each
round of data transfer.
1: Only release the bus mastership after all data transfer
is complete.
Rev. 4.00 Dec. 15, 2009 Page 280 of 1558
REJ09B0181-0400