SH7080_09 Datasheet, PDF (533/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W
Description
0
TGFA
0
R/(W)*¹ Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing conditions]
• When DMAC is activated by TGIA interrupt
• When DTC is activated by TGIA interrupt and the
DISEL bit of MRB in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the
flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and
write 0 to it.
Rev. 4.00 Dec. 15, 2009 Page 473 of 1558
REJ09B0181-0400