SH7080_09 Datasheet, PDF (248/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation
Source
DTC Vector
Vector Address
Number Offset
DTCE*¹
Transfer
Source
Transfer
Destination Priority
SSU
SSRXI
233
H'7A4
DTCERE7 SSRDR0 to Arbitrary*² High
SSRDR3
SSTXI
234
H'7A8
DTCERE6 Arbitrary*² SSTDR0 to
SSTDR3
I²C2
IITXI
238 H'7B8
DTCERE5 Arbitrary*² ICDRT
IIRXI
239
H'7BC
DTCERE4 ICDRR
Arbitrary*² Low
Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0. To leave software standby mode with an interrupt, write 0 to the
corresponding DTCE bit.
2. An external memory, a memory-mapped external device, an on-chip memory, or an on-
chip peripheral module (except DMAC, DTC, BSC, UBC, and FLASH) can be selected
as the source or destination. Note that at least either the source or destination must be
an on-chip peripheral module; transfer cannot be done among an external memory, a
memory-mapped external device, and an on-chip memory.
Rev. 4.00 Dec. 15, 2009 Page 188 of 1558
REJ09B0181-0400