SH7080_09 Datasheet, PDF (949/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
If the value of RDRF is 1 when the 8th clock rises, ORER in SSSR is set to 1, an overrun error
occurs, and reception halts. Receive operation is not possible while ORER is set to 1. To restart
reception, first clear ORER to 0.
Start
[1]
Initial setting
[2]
Read TDRE in SSSR.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[3]
No
Read SSSR
RDRF = 1?
Yes
ORER = 1?
No
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Read the TEND bit in SSSR
TEND = 1?
Yes
Clear TEND in SSSR to 0
Yes [4]
Yes ^[5]
No
[1] Initial setting:
Specify the transmit/receive data format.
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
One bit time quantum
elapsed?
Yes
Clear TE and RE in SSER to 0
No
Error processing
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
Rev. 4.00 Dec. 15, 2009 Page 889 of 1558
REJ09B0181-0400