SH7080_09 Datasheet, PDF (242/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Initial
Bit
Bit Name Value R/W Description
2, 1 ⎯
All 0
R
Reserved
These are read-only bits and cannot be modified.
0
ERR
0
R/(W)* Transfer Stop Flag
Indicates that the DTC address error or NMI interrupt
request has occurred. If a DTC address error or NMI
interrupt occurs while the DTC is active, address error
handling or NMI interrupt handling processing is executed
after the DTC has released the bus mastership. The DTC
stops in the transfer information writing state after
transferring data.
0: No interrupt occurs
1: An interrupt occurs
[Clearing condition]
• When writing 0 after reading 1
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 4.00 Dec. 15, 2009 Page 182 of 1558
REJ09B0181-0400