SH7080_09 Datasheet, PDF (1607/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
18.3.4 I²C Bus Interrupt
Enable Register (ICIER)
Page
912
913
19.3.2 A/D
950
Control/Status
Registers_0 to _2
(ADCSR_0 to ADCSR_2)
19.3.4 A/D Trigger
959
Select Registers_0 and
_1 (ADTSR_0 and
ADTSR_1)
• ADTSR_0
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name Value R/W Description
5
RIE
0
R/W Receive Interrupt Enable
RIE enables or disables the receive data full interrupt
request (IIRXI) when receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
IIRXI can be canceled by clearing the RDRF or RIE bit
to 0.
0: Receive data full interrupt request (IIRXI) are
disabled.
1: Receive data full interrupt request (IIRXI) are
enabled.
Initial
Bit
Bit Name Value R/W Description
4
NAKIE
0
R/W NACK Receive Interrupt Enable
NAKIE enables or disables the NACK
detection/arbitration lost/overrun error interrupt request
(IINAKI) when the NACKF or AL/OVE bit in ICSR is set
to 1. IINAKI can be canceled by clearing the NACKF,
AL/OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (IINAKI) is disabled.
1: NACK receive interrupt request (IINAKI) is enabled.
Table amended
Initial
Bit Bit Name Value
15
ADF
0
R/W
R/(W)*
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC is activated by an ADI interrupt
and ADDR is read
• When the DTC is activated by an ADI interrupt and
ADDR is read while the DISEL bit in the MRB
register of the DTC is cleared to 0
Table amended
Bit
7 to 4
Bit Name
TRG1S[3:0]
Initial
Value
0000
R/W Description
R/W A/D Trigger 1 Select 3 to 0
Select an external trigger, MTU2 trigger, or MTU2S
trigger to start A/D conversion for A/D module 1. In 2-
channel scan mode, these bits select an external
trigger, MTU2 trigger, or MTU2S trigger to start A/D
conversion for group 0.
0000: External trigger pin (ADTRG) input
0001: TGRA input capture/compare match on each
MTU2 channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
...
Rev. 4.00 Dec. 15, 2009 Page 1547 of 1558
REJ09B0181-0400