SH7080_09 Datasheet, PDF (946/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 17.7 shows an example of reception operation, and figure 17.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
When setting the SSU to slave mode to perform continuous reception, read SSRDR before starting
the next receive operation. If the next receive operation starts before SSRDR is read and RDRF is
cleared to 0, and SSRDR is read before reception completes, CE in SSSR is set to 1 after the
completion of reception.
In addition, if the next receive operation starts before SSRDR is read and RDRF is cleared to 0,
and SSRDR is not read until after reception completes, the receive data is discarded even though
neither CE nor ORER in SSSR is set to 1.
Rev. 4.00 Dec. 15, 2009 Page 886 of 1558
REJ09B0181-0400