SH7080_09 Datasheet, PDF (884/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the number of
transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR
with the lower eight bits. SCFDR can always be read from by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
T[4:0]
-
-
-
R[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 13 ⎯
12 to 8 T[4:0]
7 to 5 ⎯
4 to 0 R[4:0]
Initial
value
All 0
00000
All 0
00000
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Indicate the number of non-transmitted data stored in
SCFTDR. H'00 means no transmit data, and H'10
means that SCFTDR is full of transmit data.
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Indicate the number of receive data stored in SCFRDR.
H'00 means no receive data, and H'10 means that
SCFRDR full of receive data.
Rev. 4.00 Dec. 15, 2009 Page 824 of 1558
REJ09B0181-0400