SH7080_09 Datasheet, PDF (1495/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tr
Trw
Tc1
Tcw
t_AD1
Row address
t_AD1
t_AD1
Column address
t_AD1
t_AD1
READA command
Td1
Tde
Tap
t_AD1
CSn
RDWR
RASx
CASx
DQMxx
t_CSD
t_RWD
t_RASD
t_RASD
t_CASD
t_CASD
t_DQMD
D31 to D0
BS
t_BSD
t_BSD
t_CSD
t_RWD
t_DQMD
t_RDS2
t_RDH2
CKE
DACKn^*2
TENDn^*2
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.25 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1435 of 1558
REJ09B0181-0400