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SH7080_09 Datasheet, PDF (438/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family | |||
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Section 9 Bus State Controller (BSC)
9.5.15 Access to On-Chip FLASH and On-Chip RAM by CPU
Access to the on-chip FLASH for read is synchronized with IÏ clock and is executed in one clock
cycle. For details on programming and erasing, see section 23, Flash Memory.
Access to the on-chip RAM for read/write is synchronized with I Ï clock and is executed in one
clock cycle. For details, see section 25, RAM.
9.5.16 Access to On-Chip Peripheral I/O Registers by CPU
Table 9.35 shows the number of cycles required for access to the on-chip peripheral I/O registers
by the CPU.
Table 9.35 Number of Cycles for Access to On-Chip Peripheral I/O Registers
Number of Access Cycles
Write
(3 + n) Ã IÏ + (1 + m) Ã BÏ + 2 Ã PÏ
Read
(3 + n) Ã IÏ + (1 + m) Ã BÏ + 2 Ã PÏ + 2 Ã IÏ
Notes: 1. When IÏ:BÏ = 8:1, n = 0 to 7.
When IÏ:BÏ = 4:1, n = 0 to 3.
When BÏ:PÏ = 4:1, m = 0 to 3.
When IÏ:BÏ = 3:1, n = 0 to 2.
When BÏ:PÏ = 3:1, m = 0 to 2.
When IÏ:BÏ = 2:1, n = 0 to 1.
When BÏ:PÏ = 2:1, m = 0 to 1.
When IÏ:BÏ = 1:1, n = 0.
When BÏ:PÏ = 1:1, m = 0.
n and m depend on the internal execution state.
2. The clock ratio of MIÏ and MPÏ does not affect the number of access cycles.
Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus
are input and output in synchronization with rising edges of the corresponding clock signal. The L
bus, I bus, and peripheral bus are synchronized with the IÏ, BÏ, and PÏ clock, respectively. Figure
9.52 shows an example of the timing of write access to a register in 2PÏ cycle access with the
connected peripheral bus width of 16 bits when IÏ:BÏ:PÏ = 4:2:2. In access to the on-chip
peripheral I/O registers, the CPU requires three cycles of IÏ for preparation of data transfer to the I
bus after the data has been output to the L bus. After these three cycles, data can be transferred to
the I bus in synchronization with rising edges of BÏ. However, as there are two IÏ clock cycles in
a single BÏ clock cycle when IÏ: BÏ = 4:2, transfer of data from the L bus to the I bus takes (3 +
n) Ã IÏ (n = 0 to 1) (3 Ã IÏ is indicated in figure 9.52). The relation between the timing of data
output to the L bus and the rising edge of BÏ depends on the state of program execution. In the
Rev. 4.00 Dec. 15, 2009 Page 378 of 1558
REJ09B0181-0400
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