SH7080_09 Datasheet, PDF (355/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled at the falling edge of CK at the transition from the T1 or Tw
cycle to the T2 cycle.
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
CK
A29 to A0
CSn
RDWR
Read
RD
D31 to D0
Write
WRxx
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.9 Wait State Timing for Normal Space Access
(Wait State Insertion Using WAIT Signal)
Rev. 4.00 Dec. 15, 2009 Page 295 of 1558
REJ09B0181-0400