SH7080_09 Datasheet, PDF (426/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.33 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Address Mode for the SDRAM Interface (1)
Transfer from the external device with DACK to the SDRAM interface:
CMNCR.DMAIW
Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
BSC Register Setting*¹
CS3WCR.WTRP
Setting
CS3WCR.TRWL
Setting
1
0
1
1
1
2
1
3
2
0
2
1
2
2
2
3
3
0
3
1
3
2
3
3
4
0
4
1
4
2
4
3
1
0
1
1
1
2
1
3
2
0
2
1
2
2
2
3
3
0
3
1
3
2
3
3
4
0
Minimum Number of
Idle Cycles
1*²
1
2
3
1
2
3
4
2
3
4
5
3
4
5
6
1
1
2
3
1
2
3
4
2
3
4
5
3
Rev. 4.00 Dec. 15, 2009 Page 366 of 1558
REJ09B0181-0400