SH7080_09 Datasheet, PDF (977/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Initial
Bit
Bit Name Value R/W Description
0
ADZ
0
R/W General Call Address Recognition Flag
This bit is valid in slave receive mode with the I²C bus
format.
[Setting condition]
• When the general call address is detected in slave
receive mode
[Clearing condition]
• When 0 is written to ADZ after reading ADZ=1
Note: * When NACKF = 1 is detected, be sure to clear NACKF in the transfer end processing.
Until the flag is cleared, next transmission or reception cannot be started.
18.3.6 I²C Bus Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I²C bus format, if the upper seven bits of SAR match the
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
Bit: 7
Initial value: 0
R/W: R/W
6
0
R/W
5
4
3
SVA[6:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
R/W
0
FS
0
R/W
Bit
7 to 1
Bit Name
SVA[6:0]
0
FS
Initial
Value
All 0
0
R/W
R/W
R/W
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I²C bus.
Format Select
0: I²C bus format is selected
1: Clock synchronous serial format is selected
Rev. 4.00 Dec. 15, 2009 Page 917 of 1558
REJ09B0181-0400