SH7080_09 Datasheet, PDF (541/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.9 Timer Synchronous Clear Register (TSYCR)
TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and
TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCRS in
channel 3 but the MTU2 has no TSYCR.
Bit: 7
6
5
4
3
2
1
0
CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
CE0A
0
R/W Clear Enable 0A
Enables or disables counter clearing when the TGFA
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_0
1: Enables counter clearing by the TGFA flag in TSR_0
6
CE0B
0
R/W Clear Enable 0B
Enables or disables counter clearing when the TGFB
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_0
1: Enables counter clearing by the TGFB flag in TSR_0
5
CE0C
0
R/W Clear Enable 0C
Enables or disables counter clearing when the TGFC
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFC flag in TSR_0
1: Enables counter clearing by the TGFC flag in TSR_0
4
CE0D
0
R/W Clear Enable 0D
Enables or disables counter clearing when the TGFD
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFD flag in TSR_0
1: Enables counter clearing by the TGFD flag in TSR_0
Rev. 4.00 Dec. 15, 2009 Page 481 of 1558
REJ09B0181-0400