SH7080_09 Datasheet, PDF (471/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 10.10 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
⎯ Intermittent mode 16 and intermittent mode 64
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus
master whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If
the next transfer request occurs after that, the DMAC gets the bus mastership from other
bus master after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of
one unit and returns the bus mastership to other bus master. These operations are repeated
until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 10.11 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
⎯ Dual address mode
⎯ DREQ low level detection
DREQ
More than 16 or 64 Bφ
(change by the CPU's state of using bus)
Bus cycle
CPU CPU CPU DMAC DMAC CPU
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 10.11 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
Rev. 4.00 Dec. 15, 2009 Page 411 of 1558
REJ09B0181-0400