SH7080_09 Datasheet, PDF (440/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.17 Access to External Memory by CPU
Table 9.36 shows the number of cycles required for access to the external memory by the CPU. As
the table shows, the number of cycles varies with the clock ratio, the access size, the external bus
width of the LSI, and the setting for wait insertion. For details on the wait-insertion setting, see
section 9.4, Register Descriptions.
Table 9.36 Number of External Access Cycles
External Access
Bus Width Size
Write/Read
Number of Access Cycles
8 bits
Byte
Write
(1 + n) × Iφ + (3 + m) × Bφ
Read
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
Word
Write
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ
Read
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ
Longword Write
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ
Read
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ + 1 × Iφ
16 bits
Byte/Word Write
(1 + n) × Iφ + (3 + m) × Bφ
Read
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
Longword Write
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ
Read
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ
32 bits
Byte/Word/ Write
Longword _Read
(1 + n) × Iφ + (3 + m) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
Note: n:
m, o:
When Iφ:Bφ = 8:1, n = 0 to 7.
When Iφ:Bφ = 4:1, n = 0 to 3.
When Iφ:Bφ = 3:1, n = 0 to 2.
When Iφ:Bφ = 2:1, n = 0 to 1.
When Iφ:Bφ = 1:1, n = 0.
m: Wait setting, o: Wait setting + idle setting
For details, see section 9.4, Register Descriptions.
Synchronous logic and a layered bus structure have been adopted for this LSI circuit. Data on each
bus are input and output in synchronization with rising edges of the corresponding clock signal.
The L bus and I bus are synchronized with the Iφ and Bφ clocks, respectively. Figure 9.54 shows
an example of the timing of write access to a word of data over the external bus, with a bus-width
of 8 bits, when Iφ:Bφ = 2:1. Once the CPU has output the data to the L bus, data are transferred to
the I bus in synchronization with rising edges of Bφ. There are two Iφ clock cycles in a single Bφ
clock cycle when Iφ: Bφ = 2:1. Thus, when Iφ: Bφ = 2:1, data transfer from the L bus to the I bus
Rev. 4.00 Dec. 15, 2009 Page 380 of 1558
REJ09B0181-0400