SH7080_09 Datasheet, PDF (312/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
HW[1:0] 00
R/W Delay Cycles from RD and WRxx Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(2) MPX-I/O
• CS5WCR
Bit: 31 30
-
-
Initial value: 0
0
R/W: R
R
Bit: 15 14
-
-
Initial value: 0
0
R/W: R
R
29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
- SZSEL MPXW -
WW[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R R/W R/W R R/W R/W R/W
13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 22 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 252 of 1558
REJ09B0181-0400