SH7080_09 Datasheet, PDF (381/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Burst Write: A burst write occurs in the following cases in this LSI.
• Access size in writing is larger than data bus width
• 16-byte transfer in DMAC
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is
connected to a 32-bit data bus. The relationship between the access size and the number of bursts
is shown in table 9.26.
Figure 9.20 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1 to Tc3 cycles, and the WRITA command is
issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output
simultaneously with the write command. After the write command with the auto-precharge is
output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that
waits for completion of the auto-precharge induced by the WRITA command in the SDRAM.
Between the Trwl and Tap cycles, a new command will not be issued to the same bank. However,
access to another CS space or another bank in the same SDRAM space is enabled. The number of
cycles in a Trw1 cycle is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of
cycles in a Tap cycle is specified by the WTRP1 and WTRP0 bits in CS3WCR.
Rev. 4.00 Dec. 15, 2009 Page 321 of 1558
REJ09B0181-0400