SH7080_09 Datasheet, PDF (1391/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Bit
6 to 0
Section 26 Power-Down Modes
Bit Name
⎯
Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
26.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP
7
6
-
MSTP MSTP
4
3
-
-
-
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R/W R R/W R/W R R R
Initial
Bit
Bit Name Value R/W Description
7
MSTP7
0
R/W Module Stop Bit 7
When this bit is set to 1, the supply of the clock to the
RAM is halted.
0: RAM operates
1: Clock supply to RAM halted
6
MSTP6
0
R/W Module Stop Bit 6
When this bit is set to 1, the supply of the clock to the
ROM is halted.
0: ROM operates
1: Clock supply to ROM halted
5
⎯
1
R Reserved
This bit is always read as 1. The write value should
always be 1.
4
MSTP4
1
R/W Module Stop Bit 4
When this bit is set to 1, the supply of the clock to the
DTC is halted.
0: DTC operates
1: Clock supply to the DTC halted
Rev. 4.00 Dec. 15, 2009 Page 1331 of 1558
REJ09B0181-0400