SH7080_09 Datasheet, PDF (71/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
PE0/DREQ0/TIOC0A/AUDCK*4
PE1/TEND0/TIOC0B
PE2/DREQ1/TIOC0C
Vcc
PE3/TEND1/TIOC0D/AUDATA3*4
PE4/IOIS16/TIOC1A/RXD3/AUDATA2*4
PE5/CS6/CE1B/TIOC1B/TXD3/AUDATA1*4
PE6/CS7/TIOC2A/SCK3/AUDATA0*4
Vss
AVss
PF0/AN0
PF1/AN1
PF8/AN8
PF9/AN9
PF2/AN2
PF3/AN3
PF10/AN10
PF11/AN11
AVcc
PF4/AN4
PF5/AN5
PF12/AN12
PF13/AN13
AVss
PF6/AN6
PF7/AN7
PF14/AN14
PF15/AN15
AVref
AVcc
Vss
PA0/CS4/RXD0
PA1/CS5/CE1A/TXD0
PA2/A25/DREQ0/IRQ0/SCK0
PA3/A24/RXD1
Vcc
PA4/A23/TXD1
PA5/A22/DREQ1/IRQ1/SCK1
PE7/BS/TIOC2B/UBCTRG/RXD2/SSI
PE8/TIOC3A/SCK2/SSCK/TMS*³
VcL
PE9/TIOC3B/SCK3/RTS3/TRST*3
PE10/TIOC3C/TXD2/SSO/TDI*3
PE11/TIOC3D/RXD3/CTS3/TDO*3
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
133
88
134
87
135
86
136
85
137
84
138
83
139
82
140
81
141
80
142
79
143
78
144
77
145
76
146
75
147
74
148
73
149
72
150
71
151
70
152
69
153
68
154
LQFP-176
67
155
(Top view)
66
156
65
157
64
158
63
159
62
160
61
161
60
162
59
163
58
164
57
165
56
166
55
167
54
168
53
169
52
170
51
171
50
172
49
173
48
174
47
175
46
176
45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PD23/D23/IRQ7/AUDSYNC*4
PD24/D24/DREQ0/TIOC4DS
Vss
PD25/D25/DREQ1/TIOC4CS
PD26/D26/DACK0/TIOC4BS
PD27/D27/DACK1/TIOC4AS
PD28/D28/CS2/TIOC3DS
PD29/D29/CS3/TIOC3BS
PA6/CS2/TCLKA
PA7/CS3/TCLKB
PA8/RDWR/IRQ2/TCLKC
PA9/FRAME/CKE/IRQ3/TCLKD
PA10/CS0/POE4
PA11/CS1/POE5
Vcc
PA12/WRL/DQMLL/POE6
PA13/WRH/DQMLU/WE/POE7
VcL
PD30/D30/TIOC3CS/IRQOUT
PD31/D31/TIOC3AS/ADTRG
PA29/A29/IRQ3
PA28/A28/IRQ2
Vcc
PA27/A27/IRQ1
Vss
PA26/A26/IRQ0
PC25/A25
PC24/A24
PC23/A23
PC22/A22
PC21/A21
Vss
PC20/A20
PC19/A19
PC18/A18
WDTOVF
PA14/RD
Vcc (ASEMD0*2)
PB9/A21/IRQ7/ADTRG/POE8
PB8/A20/WAIT/IRQ6/SCK0
Vcc
PB7/A19/BREQ/IRQ5/TXD0
PB6/A18/BACK/IRQ4/RXD0
PB5/CASL/IRQ3/POE3
Notes: 1. This pin is fixed to VSS in the mask ROM and ROM-less versions and is used as the FWE input pin in the F-ZTAT version.
2. This pin is for the E10A emulator. It is fixed to VCC in the mask ROM and ROM-less versions and is used as the ASEMD0 input pin
in the F-ZTAT version.
3. These pin functions are only available in the F-ZTAT version (i.e., they are not available in the mask ROM and ROM-less versions).
4. These pin functions are only available in the F-ZTAT version supporting full functions of E10A (not available in normal F-ZTAT version).
Figure 1.5 Pin Assignments of SH7086
Rev. 4.00 Dec. 15, 2009 Page 11 of 1558
REJ09B0181-0400