SH7080_09 Datasheet, PDF (970/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.3.3 I²C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first and selects the transfer bit count.
Bit: 7
6
5
4
3
2
1
0
MLS
-
-
- BCWP
BC[2:0]
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
6
⎯
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
5, 4
⎯
All 1
R Reserved
These bits are always read as 1. The write value
should always be 1.
3
BCWP
1
R/W BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0.
In clock synchronous serial mode, BC should not be
modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
Rev. 4.00 Dec. 15, 2009 Page 910 of 1558
REJ09B0181-0400