SH7080_09 Datasheet, PDF (279/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Figure 9.1 shows a block diagram of the BSC.
Section 9 Bus State Controller (BSC)
BACK
BREQ
WAIT
Bus
mastership
controller
Wait
controller
CMNCR
CS0WCR
CS8WCR
CS0, CS1, CS2,
CS3, CS4, CS5,
CS6, CS7, CS8
A29 to A0,
D31 to D0
BS, RDWR, RD, WRHH,
WRHL, WRH, WRL,
RASU, RASL, CASU,
CASL, CKE, DQMxx,
AH, FRAME, CE1A,
CE1B, CE2A, CE2B,
ICIORD, ICIOWR, WE
IOIS16
Interrupt
controller
Area
controller
Memory
controller
Refresh
controller
CS0BCR
CS8BCR
SDCR
RTCSR
RTCNT
Comparator
RTCOR
[Legend]
CMNCR:
CSnWCR:
CSnBCR:
SDCR:
RTCSR:
RTCNT:
RTCOR:
Common control register
CSn space wait control register (n = 0 to 8)
CSn space bus control register (n = 0 to 8)
SDRAM control register
Refresh timer control/status register
Refresh timer counter
Refresh time constant register
BSC
Figure 9.1 Block Diagram of BSC
Internal master
module
Internal slave
module
Rev. 4.00 Dec. 15, 2009 Page 219 of 1558
REJ09B0181-0400