SH7080_09 Datasheet, PDF (883/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In clock synchronous mode, clear this bit to 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * Regardless of the input value, the CTS level
has no effect on transmit operation and the
RTS level has no effect on receive operation.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TXD) and
receive input pin (RXD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Rev. 4.00 Dec. 15, 2009 Page 823 of 1558
REJ09B0181-0400